1. Field of the Invention
The present invention relates to a Low Drop-Out (LDO) regulator, and more particularly, to an LDO regulator with over-current protection.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional LDO regulator 100. As shown in FIG. 1, the LDO regulator 100 comprises a sensing resistor RREF, a reference resistor RREF, two feedback resistors RFB1 and RFB2, a reference current source IREF, a comparator CMP, an error amplifier EA, and a transistor Q1. The transistor Q1 is a P channel Metal Semiconductor (PMOS) transistor.
The LDO regulator 100 is used to convert an input voltage source VIN to an output voltage source VOUT, for providing the output voltage source and a loading current ILOAD to the load X. The detail of operation principles of the LDO 100 is explained as follows.
The feedback resistors RFB1 and RFB2 are coupled between the output voltage source VOUT and a ground end for providing the feedback voltage VFB divided from the output voltage source VIN to the error amplifier EA. The error amplifier EA comprises a positive input end for receiving the feedback voltage VFB, a negative input end for receiving a reference voltage VREF2, and an output end for outputting the current control signal VA according to the signal received on the positive and negative input ends of the error amplifier EA. The control end (gate) of the transistor Q1 is coupled to the output end of the error amplifier EA for receiving the current control signal VA. The transistor Q1 controls the output voltage source VOUT and the loading current ILOAD according to the magnitude of the current control signal VA. More particularly, when the current control signal VA is lower, the loading current ILOAD is higher; otherwise, when the current control signal VA is higher, the loading current ILOAD is lower. Therefore, when the feedback voltage VFB is lower than the reference voltage VREF2 (for example, when the loading current drained by the load X increases), the current control signal VA outputted from the error amplifier EA turns on the transistor Q1 more for raising the output voltage VOUT. In other words, the voltage of the current control signal VA is decreased.
The reference resistor RREF is coupled between the input voltage source VIN, the reference current source IREF, and the positive input end of the comparator CMP for providing a reference voltage VREF1 to the comparator CMP. The sensing resistor RSEN is coupled between the input voltage source VIN and the negative input end of the comparator CMP for providing a sensing voltage VSEN to the operational amplifier. The comparator CMP generates a current limit control signal SC by comparing the magnitudes of the reference voltage VREF1 and the sensing voltage VSEN. That is, when the sensing voltage VSEN is higher than the reference voltage VREF1, the current limit control signal SC is logic “0” (low voltage level); otherwise, when the sensing voltage VSEN is lower than the reference voltage VREF1, the current limit control signal SC is logic “1” (high voltage level). Since the sensing resistor RSEN is serial-connected between the input voltage source VIN and the transistor Q1, the magnitude of the loading current ILOAD is limited by the comparator CMP according to the values of the sensing voltage VSEN and sensing resistor RSEN. More particularly, when the sensing voltage VSEN is lower than the reference voltage VREF1, which means the loading current ILOAD is higher than the current limit ILIMIT, the comparator CMP outputs the current limit signal SC with logic “1” to the error amplifier EA for stopping the error amplifier EA operating. In other words, when the current limit control signal SC is logic “1”, the error amplifier is disabled to keep lowering the voltage of the current limit control signal VA. In this way, the level of the transistor Q1 turned on is limited, which limits the magnitude of the loading current ILOAD.
However, since the sending resistor RSEN and the transistor Q1 are connected in series, consequently, the equivalent impedance between the input voltage source VIN and the output voltage source VOUT is increased because of existence of the sensing resistor RSEN, causing more power waste and increasing the minimal voltage difference of the input voltage source and the output voltage source of the LDO regulator 100, and therefore the efficiency of the LDO regulator is decreased.